As logic devices continue to scale down according to Moore's Law, processing challenges develop. One such challenge arises in floating gate (FG) NAND flash memory chips, which feature transistors that incorporate two gate elements, a control gate and a floating gate, to enable each transistor to assume more than one bit value. FG NAND memory forms the basis of most USB flash memory devices and memory card formats used today.
As critical dimensions of FG NAND devices shrink, the geometry of the various components becomes more challenging for manufacturers. Aspect ratios rise and uniformity, tolerance, and reliability issues proliferate. With NAND flash memory increasing in popularity as a convenient storage medium, there is a need for improved manufacturing processes to overcome scaling challenges particular to NAND flash devices.